![]() Simulate this circuit – Schematic created using CircuitLab Suppose you arrange a schematic like this: You prepare partial products, shift them relative to each other, and then just add. But, by and large, multiplier methods have a great deal of similarity with multi-digit multiplication techniques taught in grade school. The OP has updated the question in comments so the following is no longer as directly relevant as it may have been before.) (What's below was my initial prodding answer. So you'll need two half-adders and two full-adders.ĭo you think you can arrange that? General Multiplier Approach If A is the 4-bit input then: 0 A3 A2 A1 A0 0 The next lowest order bit has to perform a half-adder function. The next lowest order output bit is just a copy of \$PP_1\$'s low-order bit. Since the lowest order output bit is guaranteed to be '0', nothing is needed there. A really simple modular approach is to use a half-adder for the lowest order computational output bit and full-adders for the rest. The only remaining thing is to sum up the two 4-bit partial terms aligned correctly with the output. So the partial product generator requires zero logic. So there's no need for any AND logic, at all. And since you already know the constant is 6, these two partial products are just "lane changes" (shift left or shift right) for the bits. Referring to the sidelined discussion I gave earlier (see below), multiplying by 6 just means that two of the partial products, \$PP_1\$ and \$PP_2\$, carry a meaningful value. You are now talking about multiplying a 4-bit binary input by 0圆. I strongly recommend adding an addendum at the bottom of your question that incorporates your comment that extends your question.
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